Fri, Jun 29, 2001 at 19:56:40, eddy+public+spam (E.B. Dreger) wrote about "Re: libc_r 
locking... why?": 

> > A Token may not be enough because writes may be reordered.

AFAIK it's false for i386 architecture. Please correct me if needed.

> Here is where I want to learn more about cache coherency, inter-processor
> interrupts, and APIC programming.  I'd imagine that the latter two are
> lower-level than I'd be using, but I still want to know the "how and why"
> beneath the scenes.

Did you try to read MP chipsets white papers?


/netch

To Unsubscribe: send mail to [EMAIL PROTECTED]
with "unsubscribe freebsd-hackers" in the body of the message

Reply via email to