On Sun, Jul 01, 2001 at 03:52:56PM +0300, Valentin Nechayev wrote:
> Fri, Jun 29, 2001 at 19:56:40, eddy+public+spam (E.B. Dreger) wrote about "Re:
>libc_r locking... why?":
>
> > > A Token may not be enough because writes may be reordered.
>
> AFAIK it's false for i386 architecture. Please correct me if needed.
In -currents NOTEs I found this:
# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
# reorder). This option should not be used if you use memory mapped
# I/O device(s).
A good sign that it may be at least possible on some CPUs.
OK that's not an MP capable CPU.
What you need is an x86 guru or asume worst which will be the best
thing anyway - otherwise you can't use it on other machines and
sometimes programms get very old.
I also don't know what the following is:
# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
# K5/K6/K6-2 cpus.
> > Here is where I want to learn more about cache coherency, inter-processor
> > interrupts, and APIC programming. I'd imagine that the latter two are
> > lower-level than I'd be using, but I still want to know the "how and why"
> > beneath the scenes.
>
> Did you try to read MP chipsets white papers?
I can't say very much about coherency problems on x86 but I can
say for shure that you have to worry about this on every other MP
platform including IA64.
--
B.Walter COSMO-Project http://www.cosmo-project.de
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