On Wed, Aug 30, 2006 at 12:23:20PM +0900, Ganbold wrote:
 > Hi,
 > 
 > Thanks a lot for your patch. Your patch fixes panic, however I still see
 > bge0: firmware handshake timed out
 > bge0: link state changed to DOWN
 > messages.
 > 
 > When I tried to use Oleg's if_bge.c, rev. 1.140 in STABLE buildkernel stops:
 > 
 > mkdep -f .depend -a   -nostdinc -D_KERNEL -DKLD_MODULE -I- 
 > -DHAVE_KERNEL_OPTION_HEADERS -I. -I@ -I@/contrib/altq -I@/../include 
 > -I/usr/include -I/usr/obj/usr/src/sys/DEVIL 
 > /usr/src/sys/modules/bge/../../dev/bge/if_bge.c
 > /usr/src/sys/modules/bge/../../dev/bge/if_bge.c:2570:35: macro 
 > "VLAN_INPUT_TAG" requires 4 arguments, but only 3 given
 > mkdep: compile failed
 > *** Error code 1
 > 1 error
 > *** Error code 2
 > 1 error
 > *** Error code 2
 > mkdep: compile failed
 > *** Error code 1
 > 2 errors
 > *** Error code 2
 > 1 error
 > *** Error code 2
 > 1 error
 > 
 > I see VLAN_INPUT_TAG is defined as VLAN_INPUT_TAG(_ifp, _m, _t, 
 > _errcase) in if_vlan_var.h, rev v 1.21.2.2 with 4 arguments, however
 > new if_bge.c, rev. 1.140 uses 3 arguments.
 > Is it safe to use if_vlan_var.h, rev 1.24 and if_vlan.c, rev 1.114 only? 
 > What other patches should I use?
 > When all these changes MFC to STABLE?
 > 

You should use VLAN_INPUT_TAG_NEW macro in RELENG_6.
Anyway, here is guess work for BCM5752(obtained from OpenBSD).
Because I don't have 5752 hardware I don't know whether it works or
not. The patch is for RELENG_6(You need brgphy(4) patch too).

 > thanks,
 > 
 > Ganbold
 > 
 > Pyun YongHyeon wrote:
 > >I think your PHY was not recognized by brgphy(4). But I don't know it
 > >fixes "firmware handshake timed out" issue you've seen.
 > >Recently oleg fixed a long standing bug in bge(4). So you may also want
 > >to merge the change.(See if_bge.c, rev. 1.140)
 > >Patch generated against RELENG_6(compile tested only).
 > >

-- 
Regards,
Pyun YongHyeon
Index: if_bge.c
===================================================================
RCS file: /home/ncvs/src/sys/dev/bge/if_bge.c,v
retrieving revision 1.91.2.16
diff -u -r1.91.2.16 if_bge.c
--- if_bge.c    10 Aug 2006 11:02:14 -0000      1.91.2.16
+++ if_bge.c    30 Aug 2006 07:20:43 -0000
@@ -1007,9 +1007,26 @@
        /* Set up the PCI DMA control register. */
        if (sc->bge_pcie) {
                /* PCI Express bus */
-               dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
-                   (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
-                   (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+               uint32_t device_ctl;
+
+               /* alternative from Linux driver */
+#define DMA_CTRL_WRITE_PCIE_H20MARK_128                0x00180000
+#define DMA_CTRL_WRITE_PCIE_H20MARK_256                0x00380000
+
+               dma_rw_ctl = 0x76000000; /* XXX XXX XXX */;
+               device_ctl = pci_read_config(sc->bge_dev,
+                   BGE_PCI_CONF_DEV_CTRL, 4);
+               if ((device_ctl & 0x00e0) && 0) {
+                       /*
+                        * This clause is exactly what the Broadcom-supplied
+                        * Linux does; but given overall register programming
+                        * by bge(4), this larger DMA-write watermark
+                        * value causes BCM5721 chips to totally wedge.
+                        */
+                       dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256;
+               } else {
+                       dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128;
+               }
        } else if (sc->bge_pcix) {
                /* PCI-X bus */
                if (BGE_IS_5714_FAMILY(sc)) {
@@ -1148,22 +1165,20 @@
        CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 
        /* Enable buffer manager */
-       if (!(BGE_IS_5705_OR_BEYOND(sc))) {
-               CSR_WRITE_4(sc, BGE_BMAN_MODE,
-                   BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
+       CSR_WRITE_4(sc, BGE_BMAN_MODE,
+           BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
 
-               /* Poll for buffer manager start indication */
-               for (i = 0; i < BGE_TIMEOUT; i++) {
-                       if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
-                               break;
-                       DELAY(10);
-               }
+       /* Poll for buffer manager start indication */
+       for (i = 0; i < BGE_TIMEOUT; i++) {
+               if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
+                       break;
+               DELAY(10);
+       }
 
-               if (i == BGE_TIMEOUT) {
-                       device_printf(sc->bge_dev,
-                           "buffer manager failed to start\n");
-                       return (ENXIO);
-               }
+       if (i == BGE_TIMEOUT) {
+               device_printf(sc->bge_dev,
+                   "buffer manager failed to start\n");
+               return (ENXIO);
        }
 
        /* Enable flow-through queues */
Index: if_bgereg.h
===================================================================
RCS file: /home/ncvs/src/sys/dev/bge/if_bgereg.h,v
retrieving revision 1.36.2.7
diff -u -r1.36.2.7 if_bgereg.h
--- if_bgereg.h 10 Aug 2006 11:02:14 -0000      1.36.2.7
+++ if_bgereg.h 30 Aug 2006 07:20:43 -0000
@@ -196,6 +196,15 @@
 #define BGE_PCI_ISR_MBX_HI             0xB0
 #define BGE_PCI_ISR_MBX_LO             0xB4
 
+/* XXX:
+ * Used in PCI-Express code for 575x chips.
+ * Should be replaced with checking for a PCI config-space
+ * capability for PCI-Express, and PCI-Express standard 
+ * offsets into that capability block.
+ */
+#define BGE_PCI_CONF_DEV_CTRL          0xD8
+#define BGE_PCI_CONF_DEV_STUS          0xDA
+
 /* PCI Misc. Host control register */
 #define BGE_PCIMISCCTL_CLEAR_INTA      0x00000001
 #define BGE_PCIMISCCTL_MASK_PCI_INTR   0x00000002
@@ -305,6 +314,10 @@
 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD        0xF0000000
 # define  BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT    28
 
+/* PCI DMA Read/Write Control register, alternate usage for PCI-Express */
+#define        BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128        0x00180000 
+#define        BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256        0x00380000
+
 #define BGE_PCI_READ_BNDRY_DISABLE     0x00000000
 #define BGE_PCI_READ_BNDRY_16BYTES     0x00000100
 #define BGE_PCI_READ_BNDRY_32BYTES     0x00000200
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