Hi David & freetel-codec2, Firstly I would like to express a great appreciation for Codec 2, it's excellent to see an open-source codec in this low bitrate space!
I have a question about the performance of the algorithm on embedded hardware. A collection of friends from the local amateur radio club have got together to try build a digital radio hand-held, essentially a walkie-talkie. This is to strengthen our understanding of digital radio, and to practice our electronics engineering. I came across your algorithm when looking for free open-source codecs that could be used with a low bitrate, and I noticed that you already had this working on the SM1000 which runs an STM32F4. I understand that the CPU is also computing the baseband for TX and RX, so there is some spare headroom outside of the codec. My question is how much headroom is available, and what clock rate do you run the SM1000 at to get the necessary performance? The team and I were postulating using an STM32L4 for our radio since it offers some very low power modes which are ideal for a battery powered device, but I am concerned that the 48MHz clock will be insufficient to run Codec 2. I intend to have a separate controller handle the packet radio, so that chore is lifted off the main processor. Can you provide any insight into how Codec 2 currently performs and at which clock rate does it fail timing? Further, is there any reason to suspect that using fixed point or integer multiplication may increase the performance? Thanks again to all those involved with Codec 2; and for your work on the thesis before it David, as well as the talks you've provided to the wider community. Kind regards, Josh
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