On Fri, Jul 8, 2011 at 12:26 PM, Phil Behnke <[email protected]> wrote: > Xiaofan, > > Thanks for the help. I'm using Linux with a 2.6.38.2 custom compiled > kernel. In addition to the python application, I wrote a basic C program to > do the same thing, but I still have the same problem. Both the > python-libusb1 app and the C program are using async transfers. The maximum > isoc data rate of 24MBps should hopefully be enough, since my data from the > FPGA is at 19MBps. I've been experimenting with the data rate from the FPGA > to the FX2; I can slow the data rate way down to ~6MBps and everything works > great, but any faster than that and it starts to fail. :-/
I see. It may not be that easy to achieve 24MB/s since your host side code and the FPGA side logic need to be both good. I suggest you to post questions to libusb mailing list. I remember there are reports there about sustaining this 24MB/s isoc transfer and 35MB-45MB/s bulk transfer speed using FX2. > I'm not sure how to determine my USB chipset. You can use lspci. http://wiki.debian.org/HowToIdentifyADevice/PCI > Chris - Thanks for your help. I will check out FPGALink on your site as I > am using the Nexys2 board. (Great blog BTW; I've been using it as a > reference over the past couple months while developing this project.) > I am not familiar with FPGA but I might try this in the future with Spartan 3E (or 3Aor 3AN) Starterkit we have at work -- Xiaofan ------------------------------------------------------------------------------ All of the data generated in your IT infrastructure is seriously valuable. Why? It contains a definitive record of application performance, security threats, fraudulent activity, and more. Splunk takes this data and makes sense of it. IT sense. And common sense. http://p.sf.net/sfu/splunk-d2d-c2 _______________________________________________ Fx2lib-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/fx2lib-devel
