------- Comment #8 from bjoern dot m dot haase at web dot de 2007-12-12 18:14
-------
Created an attachment (id=14738)
--> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=14738&action=view)
patch
My new analysis leads me to the result that the key problem of this missed
optimization is a target problem: Presently we expand a divmod4 pattern that
implements the support funciton calls directly. This pattern refers directly to
hard registers. The resulting RTL is too complex for CSE and we don't identify
this optimization.
The attached patch uses the same RTL for the support function calls. Only this
RTL is now generated only after combine by a define_insn_and_split pattern. The
insn part of this pattern is valid only for pseudos so that until split. In
order to assure this, I have added a new predicate.
I have tested the patch against the atmega128 simulation target without
regressions.
2007-12-11 Bjoern Haase <[EMAIL PROTECTED]>
PR target/23726
* config/avr/predicates.md (pseudo_register_operand): Add new predicate
for pseudos
* config/avr/avr.md (divmodqi4,udivmodqi4): replace define_expand by
define_insn_and_split, delay expansion of call patterns to split pass.
(divmodhi4,udivmodhi4,divmodsi4,udivmodsi4): likewise.
--
bjoern dot m dot haase at web dot de changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #9665 is|0 |1
obsolete| |
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23726
