------- Comment #3 from alexvod at google dot com 2009-04-23 16:49 -------
Another example of sub-optimal register allocation on ARM/thumb with IRA (not
sure if this the same bug or a different one).
int func(char*);
void func2(const char*, int);
void test(char **pSignature)
{
int clazz = 0;
char *signature = *pSignature;
if (*signature == '[') {
char savedChar;
savedChar = *++signature;
clazz = func(*pSignature);
*signature = savedChar;
}
if (clazz == 0) {
func2("abc", 0);
}
*pSignature = signature;
}
It was changed by http://gcc.gnu.org/viewcvs?view=rev&revision=139590:
GCC rev139589:
test:
push {lr}
sub sp, sp, #12
mov r3, #0
str r3, [sp, #4]
.L2:
add r0, sp, #4
bl func
ldr r3, [sp, #4]
cmp r3, #12
ble .L2
add sp, sp, #12
@ sp needed for prologue
pop {pc}
GCC rev139590:
test:
push {r4, lr}
sub sp, sp, #8
mov r3, #0
add r4, sp, #4 // why put sp+4 in r4 if we can use sp+4 directly?
str r3, [sp, #4]
.L2:
mov r0, r4
bl func
ldr r3, [sp, #4]
cmp r3, #12
ble .L2
add sp, sp, #8
@ sp needed for prologue
pop {r4, pc}
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39836
