The powerpc64-unknown-linux-gnu compiler generates much worse code on the inl1130 function in the gromacs benchmark from spec 2006 when compiling for the VSX instruction set with -mcpu=power7 (or -mvsx). The code in question in not vectorizable, and in fact only uses integer and single precision floating point.
Just to be clear, the powerpc architecture originally had two sets of registers (FLOAT_REGS for scalar floating point registers and ALTIVEC_REGS for vector single precision/int registers). The VSX addition to the architecture adds a new set of scalar/vector instructions that can use registers from either register set. So, in the VSX work, I added a new register class (VSX_REGS) that is the union of the two register classes, and changed TARGET_IRA_COVER_CLASSES to return a cover class that returns VSX_REGS in the VSX case, and FLOAT_REGS/ALTIVEC_REGS in the traditional case. In the enclosed test case, it generates the following spills for the options: -O3 -ffast-math -mcpu=power7 -mvsx -maltivec: 117 stfs, 139 lfs -O3 -ffast-math -mcpu=power5 -maltivec: 80 stfs, 100 lfs -O3 -ffast-math -mcpu=power5: 80 stfs, 100 lfs Now, if I enable -fno-ira-share-spill-slots, it gets somewhat better, though obviously it uses more stack space because it can't resuse the spill stack slots: -O3 -ffast-math -mcpu=power7 -mvsx -maltivec -fno-ira-share-spill-slots: 102 stfs, 111 lfs If I don't change the IRA cover class, gromacs generates the same code, but other benchmarks that do use 64 registers won't compile correctly. -- Summary: Powerpc generates worse code for -mvsx on gromacs even though there are no VSX instructions used Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: meissner at gcc dot gnu dot org GCC build triplet: powerpc64-unknown-linux-gnu GCC host triplet: powerpc64-unknown-linux-gnu GCC target triplet: powerpc64-unknown-linux-gnu http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43413