------- Comment #9 from law at redhat dot com 2010-03-23 17:36 ------- Subject: Re: Powerpc generates worse code for -mvsx on gromacs even though there are no VSX instructions used
On 03/22/10 16:20, vmakarov at redhat dot com wrote: > ------- Comment #6 from vmakarov at redhat dot com 2010-03-22 22:20 ------- > (In reply to comment #4) > >> FWIW, I seem to get considerably worse code from mainline than you -- for -O3 >> -ffast-math -mcpu=power7 -mvsx -maltivec I get 140 stfs and 192 lfs insns >> (compared to 117& 139 respectively that you reported). >> >> > I suspect the differnce is because Mike calculated only stfs/lfs and you > stfs(x)/lfs(x). But may be I am wrong. > I think you're right. I get 117/144 for the mainline now (compared to 117/139 in the PR), so those are in the right ballpark. With the LRS bits I get 110/130, which is a clear improvement, but still nowhere near good. > >> Just for fun, I ran the same code through the a ppc compiler with the LRS >> code >> from reload-v2 and get 133:178 stfs/lsf insns, so that code clearly is >> helping, >> but it's not enough to offset the badness shown by IRA. >> >> >> I couldn't reconcile how -fno-ira-share-spill-slots would be changing the >> number of load/store insns, so I poked at that a bit. >> > Yes, I cannot understand that too. > Given how -fno-ira-share-spill-slots twiddles the bitmaps in the reload chains, it's got to either be reload register selection or reallocation occuring during reload. jeff -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43413
