http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47454
Ian Bolton <ibolton at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |WAITING Last reconfirmed| |2011.01.28 09:57:13 CC| |ibolton at gcc dot gnu.org Ever Confirmed|0 |1 --- Comment #1 from Ian Bolton <ibolton at gcc dot gnu.org> 2011-01-28 09:57:13 UTC --- (In reply to comment #0) > Created attachment 23115 [details] > testcase > > Note that register r8 is used many times, but register r2 is never used. In > thumb2 r8 is high register, its usage will cause 32bit instructions. If we > replace r8 with r2, a lot of code size will be reduced in this case. > > In arm.h REG_ALLOC_ORDER is defined as > 3, 2, 1, 0, 12, 14, 4, 5, 6, 7, 8, 10, 9, 11, 13, 15 ... > > We can see that r2 should be used before r8, but the result is not. I have thought about doing work in IRA to address this, so that we impose a higher cost for the higher registers if we have not yet ventured into them. In this particular case, the issue will be with IRA's calculated register costs. The REG_ALLOC_ORDER is only used when costs are equal, which is why the allocated order is normally roughly inline with it. R2 must be given a high cost for some reason, which causes assign_hard_reg to prefer later registers with lower costs. The IRA dump will show you the costs. If you attach it to this, we could investigate further.