http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447
--- Comment #2 from Carrot <carrot at google dot com> 2012-05-23 06:54:55 UTC --- A question about related pattern 626 (define_insn_and_split "*arm_adddi3" 627 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 628 (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") 629 (match_operand:DI 2 "s_register_operand" "r, 0"))) 630 (clobber (reg:CC CC_REGNUM))] 631 "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON" Why operand1 must be equal to operand0? Both Arm and Thumb2 have 3 register add and adc instructions.