http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54239
Bug #: 54239
Summary: Not able to generate "prefetch" (prefetch read)
instruction using -m3dnow or -mprfchw
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: venkataramanan.ku...@amd.com
Hi all,
The following are classification of prefetch instructions.
1) Prefetch instructions included by 3DNOW ISA/ new PRFCHW ISA (checked against
cpuid function 0x80000001 bit 8 of ecx register)
prefetch <MEM>
perfetchw <MEM>
2) Prefetch instructions included by SSE ISA
prefetcht0 <MEM>
prefetcht1 <MEM>
prefetcht2 <MEM>
prefetchnta <MEM>
I am trying to generate 3DNOW/PRFCHW prefetch instructions
#include <x86intrin.h>
void *p;
void
prefetchw__test (void)
{
__builtin_prefetch (p, 0, 0); //<== expecting prefetch &p
__builtin_prefetch (p, 1, 0); //<== expecting prefetchw &p
}
For the following set of options (enabled with -m3dnow and -mprfchw) the
expected instruction for prefetch read (__builtin_prefetch (p, 0, 0)) is not
generated.
1. gcc test.c -m3dnow -S
2. gcc test.c -m3dnow -mno-sse -mno-mmx -S
3. gcc test.c -S -mprfchw
4. gcc test.c -S -mprfchw -mno-sse -mno-mmx
At least for k6-2 architecture, I am not expecting the instruction prefetchnt2
to be listed with -mprfchw. (-march=k6-2 -m32 -mprfchw)
Am I missing something?
