http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53728
Uros Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
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CC| |vmakarov at gcc dot gnu.org
Component|bootstrap |rtl-optimization
--- Comment #8 from Uros Bizjak <ubizjak at gmail dot com> 2013-03-11 23:13:52
UTC ---
The difference indeed starts with IRA.
Non-debug compile declares following registers as ever live:
;; regs ever live 0[ax] 1[dx] 2[cx] 3[bx] 7[sp] 17[flags]
where debug compile declares:
;; regs ever live 0[ax] 1[dx] 2[cx] 3[bx] 4[si] 7[sp] 17[flags]
There is additional [si] register in the later compilation.
Re-categorized as generic RTL-optimization problem and added CC.
