https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63949
Bug ID: 63949 Summary: Aarch64 instruction combiner does not optimize subsi_sxth function as expected Product: gcc Version: 5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: vekumar at gcc dot gnu.org Reference: https://bugs.linaro.org/show_bug.cgi?id=863 Test case int subsi_sxth (int a, short i) { /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth #?1" } } */ return a - ((int)i << 1); } Assembly generated with GCC 5.0.0 20141114 subsi_sxth: sbfiz w1, w1, 1, 16 sub w0, w0, w1 ret Expected subw w0,w0,w1,sxth 1 Combiner Says Failed to mismatch set (reg/i:SI 0 x0) (minus:SI (reg:SI 0 x0 [ a ]) (subreg:SI (sign_extract:DI (mult:DI (reg:DI 1 x1 [ i ]) (const_int 2 [0x2])) (const_int 17 [0x11]) (const_int 0 [0])) 0))) We have a pattern that would match in aarch64.md file, but it is not recognized. (define_insn "*sub_<optab><mode>_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") (ANY_EXTRACT:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") (match_operand 2 "aarch64_pwr_imm3" "Up3")) (match_operand 3 "const_int_operand" "n") (const_int 0))))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" [(set_attr "type" "alu_ext")] )