[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-10-27
                 CC|                            |ktkachov at gcc dot gnu.org
           Assignee|unassigned at gcc dot gnu.org      |ktkachov at gcc dot 
gnu.org
     Ever confirmed|0                           |1

--- Comment #2 from ktkachov at gcc dot gnu.org ---
Confirmed.
This needs RTL checking enabled to trigger