[Bug rtl-optimization/83620] [8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1470: unable to find a register to spill with -flive-range-shrinkage --param=max-sched-ready-insns=0

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83620

--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
It looks to me that LR shrinkage pass should not move

(insn 7 22 18 2 (set (reg/v:SI 115 [ e ])
        (reg:SI 2 cx [ e ])) "pr83620.c":7 86 {*movsi_internal}
     (expr_list:REG_DEAD (reg:SI 2 cx [ e ])
        (nil)))

that includes hard register in likely spilled class (CX), since it is extending
its life across

(insn 292 3 30 2 (parallel [
            (set (reg:DI 130 [ f ])
                (ashiftrt:DI (reg:DI 37 r8 [ f ])
                    (subreg:QI (reg:SI 112 [ c ]) 0)))
            (clobber (reg:CC 17 flags))
        ]) "pr83620.c":8 580 {*ashrdi3_1}
     (expr_list:REG_DEAD (reg:SI 112 [ c ])
        (expr_list:REG_DEAD (reg:DI 37 r8 [ f ])
            (expr_list:REG_UNUSED (reg:CC 17 flags)

which needs CX.