https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81763
--- Comment #41 from Uroš Bizjak <ubizjak at gmail dot com> ---
Let's go forward with this pattern:
(define_insn "*andndi3_doubleword"
[(set (match_operand:DI 0 "register_operand" "=&r,r,r,&r")
(and:DI
(not:DI (match_operand:DI 1 "register_operand" "r,0,r,0"))
(match_operand:DI 2 "nonimmediate_operand" "rm,rm,0,rm")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
"#"
[(set_attr "isa" "bmi,bmi,bmi,*")])
(=&r,r,rm) alternative avoids matching of output to all other overlapped and
partial overlapped operands.
(=r,0,rm) alternative allows matching with op1, so we are sure output won't
*partially* overlap with op2. This is true for register and memory operands. It
can still fully overlap with register op2 in case the same reg is allocated for
op1, op2 and op3, which is OK for BMI.
(=r,r,0) alternative will prevent *partial* overlap of output with op1 in a
similar way.
(=&r,0,rm) is non-bmi alternative. Earlyclobber is needed, otherwise RA can
match op2 with op0 and op1, so the same reg is allocated for op0, op1 and op2.
If this is the case, after the split, NOT/AND sequence won't match ANDN
instruction, since NOT will change both input operands to a follow-up AND insn.
