https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071
Eric Botcazou <ebotcazou at gcc dot gnu.org> changed:
What |Removed |Added
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CC|ebotcazou at gcc dot gnu.org |
--- Comment #16 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> That's the best description of WORD_REGISTER_OPERATIONS I've seen - maybe we
> should fix the docs to be clearer?
Yes, I can add a blurb indeed.
> Also I wonder whether this means AArch64 should set it since targets like
> MIPS
> and Sparc already set it.
There seems to be a good reason against that:
/* WORD_REGISTER_OPERATIONS does not hold for AArch64.
The assigned word_mode is DImode but operations narrower than SImode
behave as 32-bit operations if using the W-form of the registers rather
than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
expects. */
#define WORD_REGISTER_OPERATIONS 0
> Thanks for fixing this. I'm still not convinced that the logic of this is
> right:
>
> if ((!WORD_REGISTER_OPERATIONS
> /* If this is a typical RISC machine, we only have to worry
> about the way loads are extended. */
> || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
> ? val_signbit_known_set_p (inner_mode, nonzero)
> : extend_op != ZERO_EXTEND)
> || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))))
> && xmode_width > inner_width)
>
> So assuming WORD_REGISTER_OPERATIONS and load_extend_op is ZERO_EXTEND, we
> fall into the (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))). But that
> effectively means that load_extend_op applies to REG_P as well as MEM_P,
> which can't be right...
You need to be sure that the upper bits in the paradoxical SUBREG are preserved
in the case of spilling to memory. In other words, you need to be sure that
zeros in the upper bits are preserved through spilling and a simple way to do
it is to require that loads be zero-extended, in case the SUBREG and not the
entire REG is spilled. reload and LRA have specific code for
WORD_REGISTER_OPERATIONS targets but I'm not sure they guarantee a full word
spill in all cases, at least reload historically hasn't I think.
