https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071
--- Comment #19 from Wilco <wilco at gcc dot gnu.org> --- (In reply to Eric Botcazou from comment #16) > > Also I wonder whether this means AArch64 should set it since targets like > > MIPS > > and Sparc already set it. > > There seems to be a good reason against that: > > /* WORD_REGISTER_OPERATIONS does not hold for AArch64. > The assigned word_mode is DImode but operations narrower than SImode > behave as 32-bit operations if using the W-form of the registers rather > than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS > expects. */ > #define WORD_REGISTER_OPERATIONS 0 How is this any different from 32-bit operations in say MIPS? The only difference seems to be that MIPS sign-extends 32-bit operations to 64 bit while AArch64 zero-extends. If that's correct for MIPS it seems that WORD_REGISTER_OPERATIONS only applies to types smaller than SImode.
