https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85038
--- Comment #1 from Peter Cordes <peter at cordes dot ca> --- Correction for AArch64: it supports addressing modes with a 64-bit base register + 32-bit index register with zero or sign extension for the 32-bit index. But not 32-bit base registers. As a hack that's better than nothing, AArch64 could use a 32-bit pointer as the index with a UXTW mode, using a zeroed register as the base (unless indexed modes have any perf downside on real AArch64 chips). But unfortunately, the architectural zero register isn't usable as the base: that encoding means the stack pointer for this instruction. ldr w1,[xzr,w2,uxtw] doesn't assemble, only x0-x30 or SP. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0801b/BABBGCAC.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/LDR_reg_gen.html describes LDR Wt, [Xn|SP, Rm{, extend {amount}}] where Rm can be an X or W register, and "extend" can be SXTW or UXTW for word regs, or LSL for X regs. (SXTX is a synonym for LSL). Any of the modes can use a left-shift amount, applied *after* extension to 64-bit. See https://community.arm.com/processors/b/blog/posts/a64-shift-and-extend-operations-operand-modifiers for details on operand-modifiers. gcc6.3 doesn't take advantage with -mabi=ilp32, and Godbolt doesn't have later AArch64 gcc. So gcc will need to know about zero-extended pointers, and the signedness of 32-bit values, to take advantage of AArch64's addressing modes for the common case of a 32-bit index. Teaching gcc to track signed/unsigned in RTL would benefit x32 and AArch64 ILP32, if I understand the situation correctly.
