https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87376
--- Comment #4 from Georg-Johann Lay <gjl at gcc dot gnu.org> --- Unfortunately, the solution from above won't work for PR65657, an issue that is basically the same: early use of explicit hard-regs and propagations from TER. Hence -fno-tree-ter can be used as work-around for both PRs. In order to avoid explicit hard-regs altogether, we'll have to use 5 new regclasses and constraints to describe the hard regs: A 1-byte class for R21 and 4 classes for R22... that span 1...4 bytes. Up to split1 there will be an ordinar mov insn from memx. split1 will split the 24-bit address into the high byte to pass in R21 and the low word to pass in Z similar to the current xload<mode>_A -> xload_<mode>_libgcc split.
