[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

[wilson at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411

--- Comment #5 from Jim Wilson <wilson at gcc dot gnu.org> ---
Author: wilson
Date: Tue Mar 19 22:33:34 2019
New Revision: 269813

URL: https://gcc.gnu.org/viewcvs?rev=269813&root=gcc&view=rev
Log:
RISC-V: Fix %lo overflow with BLKmode references.

        gcc/
        PR target/89411
        * config/riscv/riscv.c (riscv_valid_lo_sum_p): New arg x.  New locals
        align, size, offset.  Use them to handle a BLKmode reference.  Update
        comment.
        (riscv_classify_address): Pass info->offset to riscv_valid_lo_sum_p.

        gcc/testsuite/
        PR target/89411
        * gcc.target/riscv/losum-overflow.c: New test.

Added:
    trunk/gcc/testsuite/gcc.target/riscv/losum-overflow.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/riscv/riscv.c
    trunk/gcc/testsuite/ChangeLog