https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78314
Alex Bennée <alex.bennee at linaro dot org> changed:
What |Removed |Added
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CC| |alex.bennee at linaro dot org
--- Comment #26 from Alex Bennée <alex.bennee at linaro dot org> ---
Just to clear up the confusion on QEMU, we don't model any architectures that
support FPU exceptions. The ieee_6 test broke recently when we fixed writes to
the fpscr to make the exception enabling bits RAZ/WI as they should have been
all along.
Although we can use host FPU instructions (a fairly recent addition) we don't
rely on their traps and I don't believe we would have actually delivered the
trap. I suspect the test might be broken in that regard that it didn't check a
trap had actually been delivered but I can't be sure as my fortran foo is a
little lacking.
The related QEMU bug is: https://bugs.launchpad.net/qemu/+bug/1836078
