https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93505
--- Comment #15 from Jakub Jelinek <jakub at gcc dot gnu.org> --- (In reply to Jakub Jelinek from comment #14) > (In reply to Segher Boessenkool from comment #13) > > (In reply to Jakub Jelinek from comment #11) > > > and so I'd say even if we just don't fix expand_binop, this shows an > > > optimization opportunity for the rs6000 backend > > > if the rotlw instruction only uses bottom 5 bits from the last operand. > > > > Yes, but there is no easy way to express that. For shifts the mask is one > > bit *more* (in the GPRs; it is not in vectors). But we could do more in > > the .md, sure. > > But for rotlw the mask is exactly the precision? > If yes, there could be something like: > (define_insn "rotl<mode>3_cntmask" > [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") > (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") > (and:SI (match_operand:SI 2 "reg_or_cint_operand" "rn") > (match_operand:SI 3 "const_int_operand" "n")))] > "INTVAL (operands[3]) == GET_MODE_PRECISION (<MODE>mode)" > "rotl<wd>%I2 %0,%1,%<hH>2" > [(set_attr "type" "shift") > (set_attr "maybe_var_shift" "yes")]) > (though, there are various patterns with rotate and something around it, so > perhaps it would need to be done for those too). Obviously not GET_MODE_PRECISION but GET_MODE_MASK.
