https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94743
--- Comment #19 from Christophe Lyon <clyon at gcc dot gnu.org> --- (In reply to Christophe Lyon from comment #8) > Patch sent: https://gcc.gnu.org/pipermail/gcc-patches/2020-April/544872.html > > This is a simple improvement, hopefully simple enough for stage 4, yet > useful for the end-users. I have just sent an updated version of this patch: https://gcc.gnu.org/pipermail/gcc-patches/2020-May/545747.html Maybe that would be sufficient to consider this PR fixed? Indeed I fear we open a can of worms, as I've also realized that at least some Cortex-M cores save part of the FP registers when taking an interruption, the number depends on several parameters (eg secure/non-secure, ... see "Exception entry in Cortex-M33 GUG for instance https://static.docs.arm.com/100235/0002/arm_cortex_m33_dgug_100235_0002_00_en.pdf) I haven't found such documentation for Cortex-A, so I'm not sure if they have the same behaviour. I have attached a WIP patch that demonstrates local saving of FP registers as an attachment to https://gcc.gnu.org/pipermail/gcc-patches/2020-May/545754.html
