https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94962
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |jakub at gcc dot gnu.org
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
But such an instruction isn't always redundant, it really depends on what the
previous setter of the register did, whether the upper 128 bit of the 256-bit
register are already guaranteed to be zero or not.
Thus the #c1 patch looks incorrect to me, one would need peephole2s or some
combine patterns or target specific pass etc. to discover that at least for the
common cases; and it isn't something we model in the RTL patterns (what insns
guarantee which upper bits zero and what do not; and for some there can be
different choices even in the same define_insn, we could implement something
using widened registers and then there would be no guarantee etc.).
