[Bug target/96026] New: overlap register bewteen DEST and SOURCE in different machine mode

[rjiejie at me dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96026

            Bug ID: 96026
           Summary: overlap register bewteen DEST and SOURCE in different
                    machine mode
           Product: gcc
           Version: 9.3.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rjiejie at me dot com
  Target Milestone: ---

GCC seems to overlap register bewteen DEST and SOURCE in different machine
mode,

e.g. RISCV vector extension:
when VMUL > 1, most of instructions do not support with overlapped register

Is there any target hooks to control this feature ?

We can use <Constraint Modifier> ‘&’ to forbid register allocator to overlap
bewteen DEST and SOURCE,
but there are some redundancy instructions in the result code :(