https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233
--- Comment #38 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-8 branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>: https://gcc.gnu.org/g:11e0e5fa724f9f6f979abe537d6485850abfe4d9 commit r8-10530-g11e0e5fa724f9f6f979abe537d6485850abfe4d9 Author: Tamar Christina <tamar.christ...@arm.com> Date: Mon May 21 10:33:30 2018 +0000 Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a This patch adds the missing neon intrinsics for all 128 bit vector Integer modes for the three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a. gcc/ PR target/71233 * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to eor3q<mode>4. (aarch64_bcaxqv8hi): Change to bcaxq<mode>4. * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32, veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8, vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, vbcaxq_s64): New. * config/aarch64/arm_neon.h: Likewise. * config/aarch64/iterators.md (VQ_I): New. gcc/testsuite/ PR target/71233 * gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32, veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8, vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32, vbcaxq_s64): New. * gcc.target/aarch64/sha3_1.c: Likewise. * gcc.target/aarch64/sha3_2.c: Likewise. * gcc.target/aarch64/sha3_3.c: Likewise. (cherry picked from commit d21052ebd7ac9d545a26dde3229c57f872c1d5f3)