https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99593
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Priority|P3 |P1
CC| |clyon at gcc dot gnu.org,
| |ktkachov at gcc dot gnu.org
Target Milestone|--- |11.0
Last reconfirmed| |2021-03-15
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #1 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think the bug is in mismatch between predicates and constraints:
(define_insn "mve_vshlq_<supf><mode>"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
(unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w")
(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")]
VSHLQ))]
"ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
"@
vshl.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
* return neon_output_shift_immediate (\"vshl\", 'i', &operands[2],
<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);"
[(set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")]
)
imm_lshift_or_reg_neon predicate for CONST_VECTOR implies
imm_for_neon_lshift_operand, but the Dm constraint stands for
imm_for_neon_mov_operand.
--- gcc/config/arm/constraints.md.jj 2021-01-04 10:25:44.136173777 +0100
+++ gcc/config/arm/constraints.md 2021-03-15 10:49:28.660795496 +0100
@@ -32,7 +32,7 @@
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
-;; Dt, Dp, Dz, Tu, Te
+;; Ds, Dt, Dp, Dz, Tu, Te
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb,
Ra,
;; Rg, Ri
@@ -412,6 +412,14 @@ (define_constraint "Dt"
(and (match_code "const_double")
(match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
+(define_constraint "Ds"
+ "@internal
+ In ARM/Thumb-2 state a const_vector which can be used as immediate
+ in vshl instruction."
+ (and (match_code "const_vector")
+ (match_test "TARGET_32BIT
+ && imm_for_neon_lshift_operand (op, GET_MODE (op))")))
+
(define_constraint "Dp"
"@internal
In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with
bits operation"
--- gcc/config/arm/vec-common.md.jj 2021-01-29 11:54:15.650661610 +0100
+++ gcc/config/arm/vec-common.md 2021-03-15 10:50:26.570150770 +0100
@@ -299,7 +299,7 @@ (define_expand "movmisalign<mode>"
(define_insn "mve_vshlq_<supf><mode>"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
(unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w")
- (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")]
+ (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")]
VSHLQ))]
"ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
"@
fixes the ICE for me (though I really don't know what to put into dg-*
directives for the testcase, arm and aarch64 testcases are a puzzle for me).
