https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99593
--- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:009528d61c796608affd1eaa18ae31a3679eb46d commit r11-7733-g009528d61c796608affd1eaa18ae31a3679eb46d Author: Jakub Jelinek <ja...@redhat.com> Date: Fri Mar 19 13:48:44 2021 +0100 arm: Fix mve_vshlq* [PR99593] As mentioned in the PR, before the r11-6708-gbfab355012ca0f5219da8beb04f2fdaf757d34b7 change v[al]shr<mode>3 expanders were expanding the shifts by register to gen_ashl<mode>3_{,un}signed which don't support immediate CONST_VECTOR shift amounts, but now expand to mve_vshlq_<supf><mode> which does. The testcase ICEs, because the constraint doesn't match the predicate and because LRA works solely with the constraints, so it can e.g. from REG_EQUAL propagate there a CONST_VECTOR which matches the constraint but fails the predicate and only later on other passes will notice the predicate fails and ICE. Fixed by adding a constraint that matches the immediate part of the predicate. PR target/99593 * config/arm/constraints.md (Ds): New constraint. * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Use w,Ds constraint instead of w,Dm. * g++.target/arm/pr99593.C: New test.
