https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100085
--- Comment #14 from Segher Boessenkool <segher at gcc dot gnu.org> --- We *have* TImode already, but most 128-bit scalars currently use V1TImode. This often leads to reduced performance because that is not a scalar mode, does not get all optimisations we have generically for all other integer scalars. We have to do a lot of it manually, which is a lot of (combine) patterns, and we still miss almost all cases. I am not saying we should remove V1TImode. I am saying we want to use plain TImode for scalars, on newer cpus. On p8 we had V1TImode so that we could reduce the traffic between the vector register files and the GPR register file, because that was very costly on p8 (mtvsr* and mfvsr* were 5 cycles, and mtvsrdd and mfvsrld didn't even exist yet). Using V1TImode for scalars on p8 was a pretty big win. It should be a win again to use TImode on later cpus though. > And I have grave reservations about the vague plans of small/fringe minority > to > subset the PowerISA for their convenience. I don't have reservations about that. Instead, I battle that with all I can.
