https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103627
--- Comment #3 from Kewen Lin <linkw at gcc dot gnu.org> ---
Also failed with r12-0.
I looked into the ICE with -mcpu=power6 -m32 on BE, the direct reason is that
we turn off VSX flag but still leave MMA, when it wants to emit one move for
V16QI it has to use multiple word way, the generated insns are not recognized.
The reason why it turn off VSX is that TARGET_AVOID_XFORM enabled by power6:
else if (TARGET_AVOID_XFORM > 0)
msg = N_("%<-mvsx%> needs indexed addressing");
if (msg)
{
warning (0, msg);
rs6000_isa_flags &= ~ OPTION_MASK_VSX;
rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
}
I think we should check P9 vector here since Power9 supports DQ-form vector
storage access.
Even I hacked it, it will still turn off VSX in the hunk:
/* Disable VSX and Altivec silently if the user switched cpus to power7 in a
target attribute or pragma which automatically enables both options,
unless the altivec ABI was set. This is set by default for 64-bit, but
not for 32-bit. */
if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
{
TARGET_FLOAT128_TYPE = 0;
rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
| OPTION_MASK_FLOAT128_KEYWORD)
& ~rs6000_isa_flags_explicit);
}
I think it's expected because the quoted ABI change.
So the question is that when we disable VSX, can we still allow MMA?
As searching in ISA3.1, it says: "SIMD is a requirement for MMA." So I think
the answer is no. Not sure why we don't have one option P10 VECTOR like
existing P8 and P9 VECTOR, I'm going to use P9 VECTOR as one guard for MMA for
now.
