https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104698
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Michael Meissner <meiss...@gcc.gnu.org>: https://gcc.gnu.org/g:1301d7f647c7ac40da7f910aa6e790205e34bb8b commit r12-7501-g1301d7f647c7ac40da7f910aa6e790205e34bb8b Author: Michael Meissner <meiss...@linux.ibm.com> Date: Sat Mar 5 00:01:52 2022 -0500 Optimize signed DImode -> TImode on power10. On power10, GCC tries to optimize the signed conversion from DImode to TImode by using the vextsd2q instruction. However to generate this instruction, it would have to generate 3 direct moves (1 from the GPR registers to the altivec registers, and 2 from the altivec registers to the GPR register). This patch generates the shift right immediate instruction to do the conversion if the target/source registers ares GPR registers like it does on earlier systems. If the target/source registers are Altivec registers, it will generate the vextsd2q instruction. 2022-03-05 Michael Meissner <meiss...@linux.ibm.com> gcc/ PR target/104698 * config/rs6000/vsx.md (UNSPEC_MTVSRD_DITI_W1): Delete. (mtvsrdd_diti_w1): Delete. (extendditi2): Convert from define_expand to define_insn_and_split. Replace with code to deal with both GPR registers and with altivec registers. gcc/testsuite/ PR target/104698 * gcc.target/powerpc/pr104698-1.c: New test. * gcc.target/powerpc/pr104698-2.c: New test.
