[Bug target/105066] GCC thinks pinsrw xmm, mem, 0 requires SSE4.1, not SSE2? _mm_loadu_si16 bounces through integer reg

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuho...@gcc.gnu.org>:

https://gcc.gnu.org/g:e4352a0fee49441a32d12e8d8b98c425cfed4a86

commit r12-7841-ge4352a0fee49441a32d12e8d8b98c425cfed4a86
Author: liuhongt <hongtao....@intel.com>
Date:   Mon Mar 28 11:12:37 2022 +0800

    Fix typo in vec_setv8hi_0.

    pinsrw is available for both reg and mem operand under sse2.
    pextrw requires sse4.1 for mem operands.

    The patch change attr "isa" for pinsrw mem alternative from sse4_noavx
    to noavx, will enable below optimization.

    -        movzwl  (%rdi), %eax
             pxor    %xmm1, %xmm1
    -        pinsrw  $0, %eax, %xmm1
    +        pinsrw  $0, (%rdi), %xmm1
             movdqa  %xmm1, %xmm0

    gcc/ChangeLog:

            PR target/105066
            * config/i386/sse.md (vec_set<mode>_0): Change attr "isa" of
            alternative 4 from sse4_noavx to noavx.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr105066.c: New test.