[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602

--- Comment #15 from Jeffrey A. Law <law at gcc dot gnu.org> ---
THe hope is the shift 6 combines with the first shift you emit for

(set (reg:DI 137)
    (and:DI (reg:DI 138)
        (const_int 274877906880 [0x3fffffffc0])))

Conceptually this is similar to creating bridge patterns for the combiner.