https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602
--- Comment #25 from Jeffrey A. Law <law at gcc dot gnu.org> --- To outline what we were thinking. Yes, it's possible that 4->3 combinations aren't supported. I'd have to sit down with the combine sources to be sure. So the alternate approach we came up with was to mimick ZBS's ability to load up single bit constants with a define_insn_and_split, obviously splitting it into a constant load + shift unconditionally if it's still around post-combine. That's going to lead into a bigger question about constant loads. Right now we tend to break them down during expansion. The advantage of that is the components become CSE candidates. The downside is it will tend to inhibit instruction combination as we've seen in this case. I don't have a good answer on the best approach.
