https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108240
--- Comment #2 from Kewen Lin <linkw at gcc dot gnu.org> ---
Well, there are two issues here:
1) the ICE itself, it's independent of option powerpc64 handling, without the
culprit commit r13-4894 but with an explicit option -m64, the ICE is still
reproducible. So this exposes one latent bug.
When specifying -mcpu=401, it uses the default flag OPTION_MASK_SOFT_FLOAT
(soft-float), it means there is no hard-float support. But specifying the
undocumented option -mmodulo, it means to act like power9 (setting all ISA3.0
flags excepting for some -mno-xxx) as the code:
if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
It results in one unexpected state that we don't have hard-float support but we
still have P9 vector supports (of coz. VSX). Later when expanding SFmode smul,
it tries to use wider mode KFmode for the multiplication then ICE.
Currently we have some checks on the co-existence between TARGET_VSX and
!TARGET_HARD_FLOAT, I think we also need to extend it to cover those options
which can enable VSX later:
if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
...
else
rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
}
else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
If we have !TARGET_HARD_FLOAT and any of TARGET_P9_VECTOR, TARGET_MODULO,
TARGET_P9_MISC, TARGET_P9_MINMAX, TARGET_P8_VECTOR, TARGET_DIRECT_MOVE,
TARGET_CRYPTO, we are pretending there is one explicit -mno-vsx:
rs6000_isa_flags &= ~ OPTION_MASK_VSX;
rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
