https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109116
Bug ID: 109116
Summary: vector_pair register allocation bug
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: chip.kerchner at ibm dot com
Target Milestone: ---
There seems to be a bug in the register allocator when using a __vector_pair.
GCC didn't choose a register for the load that served the later instruction.
With this testcase
```
#include <altivec.h>
#if !__has_builtin(__builtin_vsx_disassemble_pair)
#define __builtin_vsx_disassemble_pair __builtin_mma_disassemble_pair
#endif
int main() {
float A[8] = { float(1), float(2), float(3), float(4),
float(5), float(6), float(7), float(8) };
__vector_pair P;
__vector_quad Q;
vector float B, C[2], D[4];
__builtin_mma_xxsetaccz(&Q);
P = *reinterpret_cast<__vector_pair *>(A);
B = *reinterpret_cast<vector float *>(A);
__builtin_vsx_disassemble_pair((void*)(C), &P);
__builtin_mma_xvf32gerpp(&Q, reinterpret_cast<__vector unsigned char>(C[0]),
reinterpret_cast<__vector unsigned char>(B));
__builtin_mma_xvf32gerpp(&Q, reinterpret_cast<__vector unsigned char>(C[1]),
reinterpret_cast<__vector unsigned char>(B));
__builtin_mma_disassemble_acc((void *)D, &Q);
return int(D[0][0]);
}
```
It produces an output with extra (unneeded) register moves.
```
plxvp 12,.LANCHOR0@pcrel
xxsetaccz 0
plxv 33,.LC1@pcrel
xxlor 45,13,13
xxlor 32,12,12
xvf32gerpp 0,45,33
xvf32gerpp 0,32,33
xxmfacc 0
```
