[Bug tree-optimization/110897] RISC-V: Fail to vectorize shift

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897

--- Comment #16 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Richard Biener from comment #15)
> Well, the question is why we arrive here with the two different vector types.
> Can you tell me a relevant cc1 compiler command like for a x86->riscv cross
> that exposes the issue?

Thanks for taking care of this issue.

The RISC-V cc1 command:

cc1 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable

For ARM SVE:

-march=armv8-a+sve -O3

This issue is exposed in both RISC-V and ARM.

code:

#include <stdint-gcc.h>

#define TEST2_TYPE(TYPE)                                        \
  __attribute__((noipa))                                        \
  void vshiftr_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)      \
  {                                                             \
    for (int i = 0; i < n; i++)                                 \
      dst[i] = (a[i]) >> b[i];                                  \
  }

#define TEST_ALL()      \
 TEST2_TYPE(uint16_t)   \

TEST_ALL()