https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109279
--- Comment #18 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #17)
> (In reply to Vineet Gupta from comment #16)
> > > Which is what this produces:
> > > ```
> > > long long f(void)
> > > {
> > > unsigned t = 16843009;
> > > long long t1 = t;
> > > long long t2 = ((unsigned long long )t) << 32;
> > > asm("":"+r"(t1));
> > > return t1 | t2;
> > > }
> > > ```
> > li a0,16842752
> > addi a0,a0,257
> > li a5,16842752
> > slli a0,a0,32
> > addi a5,a5,257
> > or a0,a5,a0
> > ret
>
> This is again IRA inflicted pain (similar to [PR110748]).
> IRA seems to be undoing split1 since we have 2 insn sequences to synthesize
> the constant pieces. This explains why the problem got exacerbated with
> commit 0530254413f8 ("riscv: relax splitter restrictions for creating
> pseudos") since now different regs are used to create parts of const, vs 1
> reg being repeatedly used for assembling a const (fooling IRA's equivalent
> replacement logic).
After commit
2023-08-18 a047513c9222 RISC-V: Enable pressure-aware scheduling by
default.
the test above has improved.
li a5,16842752
addi a5,a5,257
mv a0,a5
slli a5,a5,32
or a0,a0,a5
ret
