https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112450
--- Comment #5 from JuzheZhong <juzhe.zhong at rivai dot ai> --- (In reply to Richard Biener from comment #4) > (In reply to JuzheZhong from comment #1) > > Oh. I see we have cond_xxx pattern for VLS modes. > > > > like V64HImdoe. But we don't support partial vectorization for VLS modes. > > > > VLS modes are supposed to used as SIMD GNU vectorization. > > > > As long as COND_XXX is enabled, loop vectorizer considers target support > > partial > > vectorization with mask and since no while_ult, then go through AVX512 > > partial vectorization. > > I think the bug is in the AVX512 code where it probably lacks some guards. > But in theory even with RVV you can do mask based vectorization of > partial loops, the AVX512 code doesn't require .WHILE_ULT but instead > uses regular compares. > > I don't think you should work around this by disabling RVV patterns here. > > I can have a look later what happens. > > > It seems that for conditional operations, I should use backend RTL PASS to > > walk around that. Thanks a lot Richi. I was about to add disable cond_xxx pattern or add cond_len_xxx pattern to walk around this issue. Actually, we always apply partial vectorization on VLA modes. We always use VLS modes on SIMD GNU vectorization. We enable cond_xxx for VLS modes to handle conditional operation which makes use of match.pd vectorizations. Here is the example: https://godbolt.org/z/csx995anE You can see with cond_div on VLS modes, we can have much better codegen. Anyway, really appreciate you take care of this issue!
