https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481
--- Comment #12 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Andrew Stubbs <a...@gcc.gnu.org>: https://gcc.gnu.org/g:948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3 commit r14-5453-g948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3 Author: Andrew Stubbs <a...@codesourcery.com> Date: Tue Nov 14 16:07:37 2023 +0000 Fix ICE generating uniform vector masks Most targets have an "and" instructions for their vector mask size, but RISC-V only has DImode "and". Fixed by allowing wider instruction modes. gcc/ChangeLog: PR target/112481 * expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.