https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113538
Bug ID: 113538
Summary: [RISC-V] --param=riscv-vector-abi will fail some cases
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: yanzhang.wang at intel dot com
Target Milestone: ---
When removing the riscv-vector-abi, I found some cases failed. We can test it
by passing the arg to the tests like,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over
-zvfhmin.c
index 1d82cc8de2d..0725ca69222 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 --param=riscv-vector-abi"
} */
#include "riscv_vector.h"
The test result will be,
=== gcc tests ===
Schedule of variations:
riscv-sim/-march=rv64gcv_zvfh/-mabi=lp64d/-mcmodel=medlow
Running target riscv-sim/-march=rv64gcv_zvfh/-mabi=lp64d/-mcmodel=medlow
Using /mnt/install/toolchains/gnu/share/dejagnu/baseboards/riscv-sim.exp as
board description file for target.
Using /mnt/install/toolchains/gnu/share/dejagnu/config/sim.exp as generic
interface file for target.
Using /mnt/install/toolchains/gnu/share/dejagnu/baseboards/basic-sim.exp as
board description file for target.
Using
/home/yanzhang/workspace/toolchains/gnu/gcc/gcc/testsuite/config/default.exp as
tool-and-target-specific interface fil
e.
Running
/home/yanzhang/workspace/toolchains/gnu/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
...
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e16,\\s*mf4,\\s*t
[au],\\s*m[au] 8
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e16,\\s*mf2,\\s*t
[au],\\s*m[au] 2
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vle16\\.v\\s+v[0-9]+,\\s*0\\([0-9ax]+\\) 7
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vse16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 6
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl1re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl2re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl4re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 3
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl8re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs2r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs4r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 3
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs8r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 5
The failed test cases almost in rvv/base with same reason.
GCC commit: 57f611604e8bab67af6c0bcfe6ea88c001408412
