https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110960
Michael Meissner <meissner at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |meissner at gcc dot gnu.org
--- Comment #12 from Michael Meissner <meissner at gcc dot gnu.org> ---
The test case actually shows on power8 GCC was generating incorrect code, and
power9 is actually doing the right thing. But the test case was written
assuming the previous behavior was correct.
TL;DNR answer power8 generated STVX instead of STXVD2VX. Power9 generates
STXV.
To explain what the issue is, we need to go back in history.
PowerPC processors (and Power before it) were originally designed for big
endian environments. The Altivec instruction set had limited vector save and
load instructions (STVX and LVX) which ignored the bottom 4 bits of the
address. STVX and LVX did the correct byte swapping if the PowerPC was running
in little endian mode.
When power7 came out with the VSX instruction set, the vector save and load
instructions (STXVD2X, STXV4X, LXVD2X, and LXV4X) were added. These
instructions allowed saving and loading all 64 VSX registers (32 registers that
overlapped with floating point registers, and 32 registers that overlapped with
traditional Altivec registers). However, these instructions only store and
load values using big endian ordering.
After the power8 came out, the PowerPC Linux systems were moved from being big
endian to little endian. This meant that after doing a vector load
instruction, we had to do explicit byte swapping, and before a vector save we
had to do the byte swapping of the value before doing the save.
We added an optimization to GCC that in the special case of storing/loading
temporaries on the stack, we would use the Altivec instructions STVX and LVX
and elimiante the byte swapping instructions since we could insure that all
temporaries were correctly aligned. But we couldn't use STVX and LVX in
general due to these instructions ignoring the bottom 4 bits of the address and
they restricted the vector registers to just the VSX registers that overlap
with the Altivec registers.
When power9 came out, we added new vector store and load instructions (STXV,
STXVX, LXV, and LXVX) that did the correct byte swapping on little endian
systems. GCC now generates these instructions and eliminates the special code
to use the Altivec STVX and LVX instructions.
In the test case, VerifyVecEqToActual takes 2 vector arguments, and creates 2
16 byte arrays, and stores each vector into the array. It uses
reinterpret_cast to convert this into a store instruction.
However, since the temporary is on the stack, on power8 this uses the Altivec
STVX instruction and it gets byte swapped.
