[Bug tree-optimization/51492] vectorizer does not support saturated arithmetic patterns

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51492

--- Comment #21 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:34ed2b4593fa98b613632d0dde30b6ba3e7ecad9

commit r15-642-g34ed2b4593fa98b613632d0dde30b6ba3e7ecad9
Author: Pan Li <pan2...@intel.com>
Date:   Fri May 17 18:49:46 2024 +0800

    RISC-V: Implement IFN SAT_ADD for both the scalar and vector

    The patch implement the SAT_ADD in the riscv backend as the
    sample for both the scalar and vector.  Given below vector
    as example:

    void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
    {
      unsigned i;

      for (i = 0; i < n; i++)
        out[i] = (x[i] + y[i]) | (- (uint64_t)((uint64_t)(x[i] + y[i]) <
x[i]));
    }

    Before this patch:
    vec_sat_add_u64:
      ...
      vsetvli a5,a3,e64,m1,ta,ma
      vle64.v v0,0(a1)
      vle64.v v1,0(a2)
      slli    a4,a5,3
      sub     a3,a3,a5
      add     a1,a1,a4
      add     a2,a2,a4
      vadd.vv v1,v0,v1
      vmsgtu.vv       v0,v0,v1
      vmerge.vim      v1,v1,-1,v0
      vse64.v v1,0(a0)
      ...

    After this patch:
    vec_sat_add_u64:
      ...
      vsetvli a5,a3,e64,m1,ta,ma
      vle64.v v1,0(a1)
      vle64.v v2,0(a2)
      slli    a4,a5,3
      sub     a3,a3,a5
      add     a1,a1,a4
      add     a2,a2,a4
      vsaddu.vv       v1,v1,v2  <=  Vector Single-Width Saturating Add
      vse64.v v1,0(a0)
      ...

    The below test suites are passed for this patch.
    * The riscv fully regression tests.
    * The aarch64 fully regression tests.
    * The x86 bootstrap tests.
    * The x86 fully regression tests.

            PR target/51492
            PR target/112600

    gcc/ChangeLog:

            * config/riscv/autovec.md (usadd<mode>3): New pattern expand for
            the unsigned SAT_ADD in vector mode.
            * config/riscv/riscv-protos.h (riscv_expand_usadd): New func decl
            to expand usadd<mode>3 pattern.
            (expand_vec_usadd): Ditto but for vector.
            * config/riscv/riscv-v.cc (emit_vec_saddu): New func impl to emit
            the vsadd insn.
            (expand_vec_usadd): New func impl to expand usadd<mode>3 for
vector.
            * config/riscv/riscv.cc (riscv_expand_usadd): New func impl to
            expand usadd<mode>3 for scalar.
            * config/riscv/riscv.md (usadd<mode>3): New pattern expand for
            the unsigned SAT_ADD in scalar mode.
            * config/riscv/vector.md: Allow VLS mode for vsaddu.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: New test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: New test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: New test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: New test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: New test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: New
test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: New
test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: New
test.
            * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: New
test.
            * gcc.target/riscv/sat_arith.h: New test.
            * gcc.target/riscv/sat_u_add-1.c: New test.
            * gcc.target/riscv/sat_u_add-2.c: New test.
            * gcc.target/riscv/sat_u_add-3.c: New test.
            * gcc.target/riscv/sat_u_add-4.c: New test.
            * gcc.target/riscv/sat_u_add-run-1.c: New test.
            * gcc.target/riscv/sat_u_add-run-2.c: New test.
            * gcc.target/riscv/sat_u_add-run-3.c: New test.
            * gcc.target/riscv/sat_u_add-run-4.c: New test.
            * gcc.target/riscv/scalar_sat_binary.h: New test.

    Signed-off-by: Pan Li <pan2...@intel.com>