https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-14 branch has been updated by Uros Bizjak <u...@gcc.gnu.org>: https://gcc.gnu.org/g:ec92744de552303a1424085203e1311bd9146f21 commit r14-10264-gec92744de552303a1424085203e1311bd9146f21 Author: Uros Bizjak <ubiz...@gmail.com> Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with invalid RTX: [(set (match_operand:DI 0 "register_operand" "=c") (sign_extend:DI (match_operator:SI 3 "divmod_operator" [(match_operand:DI 1 "register_operand" "a") (match_operand:DI 2 "register_operand" "b")]))) (clobber (reg:DI 23)) (clobber (reg:DI 28))] where SImode divmod_operator (div,mod,udiv,umod) has DImode operands. Wrap input operand with truncate:SI to make machine modes consistent. PR target/115297 gcc/ChangeLog: * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode operands 3 and 4 with truncate:SI RTX. (*divmodsi_internal_er): Ditto for operands 1 and 2. (*divmodsi_internal_er_1): Ditto. (*divmodsi_internal): Ditto. * config/alpha/constraints.md ("b"): Correct register number in the description. gcc/testsuite/ChangeLog: * gcc.target/alpha/pr115297.c: New test. (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)
