https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115763
Bug ID: 115763
Summary: RISC-V: Use wrong SEW for vfmv.v.f when -march only
has zvfhmin
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sh.chiang04 at gmail dot com
Target Milestone: ---
The vfmv.v.f use SEW=16, if -march=rv64gcv_zvfhmin. And Zvfhmin only allow
SEW=16 for conversions instruction.
Zvfhmin extension link:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#184-zvfhmin-vector-extension-for-minimal-half-precision-floating-point
The following test is extract from
gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c (fail item is
"TEST2 (NAME##_f16_f16, _Float16, _Float16)")
compiler option:
-mabi=lp64d -march=rv64gcv_zfh_zvfhmin -O3 -ftree-vectorize
-mrvv-vector-bits=scalable -fno-vect-cost-model
testcase:
void test_f16_f16_f32_2 (_Float16 *dest, _Float16 bias) {
dest[0] = bias;
dest[1] = bias;
}
Assembly:
test_f16_f16_f32_2:
vsetivli zero,2,e16,mf4,ta,ma // Set SEW=16
vfmv.v.f v1,fa0 // vfmv.v.f can't use SEW=16
vse16.v v1,0(a0)
ret
