https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #341 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Kazumoto Kojima from comment #338) > (In reply to Oleg Endo from comment #337) > > (In reply to Kazumoto Kojima from comment #334) > > > Created attachment 59216 [details] > > > a patch to fix ICE in c#331 > > > > > > The patch preallocates R0 for those Sid memory patterns so as to shorten > > > the > > > live range of R0. Tested target libgcc and libstdc++v3 build and c > > > testsuilte only. > > > > I guess at some points the mem loads will start to fail, too? > > Hypothetically we will need to do this for every insn that has the R0 > > restriction? > > Yes, I added movsf_ie_load_mem_index because I think that it will fail at > some high R0 pressure situation. I've added your patch to the pile in https://github.com/olegendo/gcc/commits/devel/sh-lra/ > I have no idea for other cases, though. In any case, it may prove the need > for the R0 specific pass. Do you have any idea how that might work? The only thing I can think of right now is to remove R0 from list of allocatable registers and add an RTL pass before RA which will insert "pseudo -> R0" before R0 constrained insns and "R0 -> pseudo" after constrained insns. I think this should be almost bullet-proof, but at the expense of potentially losing one register (R0).
