https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #349 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Kazumoto Kojima from comment #345) > (In reply to Oleg Endo from comment #341) > > Do you have any idea how that might work? The only thing I can think of > > right now is to remove R0 from list of allocatable registers and add an RTL > > pass before RA which will insert "pseudo -> R0" before R0 constrained insns > > and "R0 -> pseudo" after constrained insns. I think this should be almost > > bullet-proof, but at the expense of potentially losing one register (R0). > > No, I don't have any specific idea, though I was envisioning the approach > what you suggested. Actually, the additional R0-clobber patterns that we have so far, it doesn't look too bad. Of course it would be better if it can be avoided completely. But if it's just for the loads and stores as it is now, I guess it could be fine as-is. However, I've been browsing some older PRs and this idea of the R0 specific pass has been floating around for a while. It might have the potential to improve some of the other R0-related issues, e.g. PR 64785.
