[Bug target/118140] [15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118140

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2024-12-20
            Summary|[15 Regression] RISC-V:     |[15 Regression] RISC-V:
                   |Miscompile with             |Miscompile with
                   |-march=rv64gcv_zvl256b -O3  |-march=rv64gcv_zvl256b -O3
                   |since r15-3992-g698e0ec89bc |
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Patrick O'Neill from comment #5)
> That worked, re-bisecting now.

Thanks